Instructions

Encoding Instructions as Bit Patterns

A CPU can only execute instructions that are written in machine code... a series of binary digits. If you write a program in VB.net (or any other high level language), it must first be translated into machine code by a compiler. (Code written in assembly language will be translated by an assembler).

In machine code the instructions are usually made up of 2 parts:

The CPU uses the operation code to decide what action to take with the second part, which is usually an address in memory where data is stored.

For example, an instruction could be made up of 8 bits, the first 3 representing the operation code and the remaining 5 representing the memory address...

Each operation code will represent a different instruction, for example:


A particular CPU will be designed to process a particular set of machine code instructions and will know:

The table below represents 9 memory addresses. Address 00000 holds an instruction (using 8 bits) and address 00100 holds some data. The CPU would follow the instruction and ADD the value in memory location 00100 to the accumulator.

How does a computer distinguish between Instructions & Data?

In the Von Neumann architecture (used by most computers) memory locations are used to store both program instructions and data. The CPU cannot therefore distinguish between instructions and data just by reading the contents of memory since they are both just bit patterns.

However, when a program is actually running the CPU does distinguish between them, based on which part of the fetch-execute cycle the memory address is accessed.

When a program is first started, the program counter in the CPU should be set to the memory location of the first instruction. If it is instead pointed to a memory address that contains data (either by mistake or because an instruction has somehow been overwritten by data) then the program would fail to run correctly because the CPU would try and interpret the data as an instruction.

For more information research the LMC or RISC.