RISC - Example

RISC (Reduced Instruction Set Computer) has fewer cycles per instruction that a CISC (Complex Instruction Set Computer). It is said that the ARM processors are based on this concept and some of the devices where we might find ARM processors are: iPads, smartphones and other Andriod devices.

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The object of this simulator is to show you how a modern computer might work. There are lots of things it does not do - a real implementation would have a wider memory bus and be loading several instructions at once. It would also have 32 or 64 bit registers for address calculation and arithmetic. We are using 16 bits words both for simplicity and to get a reasonable amount of memory on the screen. We also don't have interrupts, an operating system or a user mode (i.e. protection) and we do not overlap the execution of instructions (pipelining).

The simulation has a main "B" bus that interconnects all the components and a smaller "A" bus (on the left) that connects the registers to the ALU (Arithmetic and Logic Unit). There is a hidden bus that connects the registers (and the flags register) and none of the control logic is shown. You have to imagine the Control Unit having wires connecting to and controlling all the other components.

The flags register holds the result of the last ALU operation - negative (N), zero (Z), carry (C) and overflow (V). Overflow means overflow for a 2's complement operation whereas Carry means overflow for the same operation seen as an unsigned operation. For the shift operations Carry holds the last bit shifted out and for subtract Carry is "not borrow" (so it is the equivalent of negating the second number and adding). Instructions which do not use the ALU do not alter the flags and neither do address calculations (ADD and SUB to SP). You have to imagine links from the ALU to the flag bits and from the flag bits to the Control Unit (so the conditional branches can be executed).

Almost everything is based on 16 bit words. The Assembler shows signed (2's complement) in memory by default but there is an option to show memory and Registers 0-7 in unsigned or hex (and memory in binary). Output to device 4 is treated as signed but you can output unsigned (device 5), hex (device 6) or character (device 7). You can input hex as 0xnnnn everywhere a number is expected.

As well as inputting a program into the Assembly Language area you can input numbers into the Program Counter and directly into memory. When you Submit the Assembly Language a memory clear and a reset are done and the program is assembled into memory.

There is an instruction list and some other notes at RISC Instruction Set. The instruction set is loosely based on the ARM 16bit instruction set but with some optimisations for the smaller address range. E.g. ARM has no direct conditional branches (they are all relative) and does not have a direct ADD and SUB.

The information above was taken from RISC Help - courtesy of Peter Higginson

View a short video of the RISC in actionhere

Access an online simultaor here: RISC Simulator

Download the Instruction Set here.